* A Mux converts N inputs to 1 output, selecting one of them
* $log_2(n)$ control inputs are required
* Q: Using a sum of products formula and gates with 2 inputs, and assume that each gate has a delay of 1ps, what is the delay of a 4 to 1 Mux?
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## Drawback
* Logic circuits grows larger nonlinearly
* Decoders are 2 wide for 1 input, 4 wide for 2, 8 wide for 3...
* And a multiplexor will grow deeper
* So silicon costs and delays grow too fast to ignore, even as transistor density improves
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## Meaning?
* If performance is a concern, you will always need to know architecture
* Otherwise, it won't be clear how to fix bad code
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## The Final
* Uploaded a version of quiz1 and the midterm with marked answers to the files section of canvas
* Mostly so you stop bothering me, I don't believe that studying answers is a good idea
* Will hold office hours next week at the usual time
* Unless people tell me that some other time is better
* Post public questions on piazza
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## How not to Open-Ended
Q: Why does transposing a matrix make matrix multiplication faster on our CPUs? Only partial credit will be given for vague answers.
A: Because transposed matrix gets multiplied faster.